Topic 2  Sequential Logic Systems

What is a sequential circuit?

We have looked at combinational logic systems in which the output was determined by the combinations of one or more inputs.  The output state at any time is dependent on the state of the inputs.  In a sequential circuit, the output is dependent on:

• The current input to the circuit;

• The previous inputs to the circuit.

In effect the circuit has a memory.

Sequential circuits are the basic building blocks of:

• Counters;

• Shift registers;

• Memories.

  In synchronous sequential circuits, changes in output do not occur immediately there is a change in input, but the next time there is a clock pulse.  In asynchronous circuits the next stage is triggered by the completion of the previous stage without reference to a clock pulse.

Clock pulses are square wave oscillations that are produced by a pulse generator that can be based on two kinds of circuit:

• Astable generators produce trains of square waves;

• Monostables produce single pulses.

Circuits are triggered in one of two ways:

• Level triggering in which the changes occur when the level of the pulse is either at 0 or 1.

• Edge triggering in which the change occurs as the clock pulse rises from 0 to 1(rising or positive edge) or from 1 to 0 (falling or negative edge).

  The diagram shows the idea.

Level sensitive devices are often referred to as latches, while edge triggered devices are called flip-flops.  Pulses can be provided manually with switches, but they can provide spurious pulses due to bounce.  They can be de-bounced using a Schmitt trigger, which also can be used to clean up noisy signals.

Question 1 What is the difference between pulses produced by a monostable and an astable?  ANSWER

Question 2 What is the behaviour you would expect from a synchronous falling edge triggered flip-flop?  ANSWER

Click HERE to see some important definitions.

Bistable Latches

Bistables have two stable states; one output remains high while the other remains low.  These are complementary states.  The situation remains until an external input signal such as a clock pulse switches the complimentary states over.

We can use two NAND gates to produce an S-bar - R-bar latch.  The circuit diagram is shown below in below.

There are two inputs to the latch, the set, S-bar, and the reset, R-bar.  There are two output states, Q and Q-bar which are complementary to each other.  This means that when Q = 0, Q-bar = 1, and vice versa.  The common symbol for the latch is not the circuit diagram above, but either of the alternatives shown.

This bistable is the industry standard, made from NAND gates.  We say that its inputs are active-low which means that the state changes when the inputs go low.

We can draw up a truth table, often called a transition table for the circuit.  We can also show what is happening in a timing diagram, which is three voltage-time graphs stacked one on top of the other.

When S-bar falls from 1 to 0, there is no effect until the R-bar falls from 1 to 0.  Then the output Q changes from 1 to 0.  Then R-bar goes to 1, but there is no change in Q until S-bar goes to 1.

This  latch is a circuit that can be used to de-bounce a switch, cleaning its action to get rid of unwanted pulses.  The layout is shown in the diagram:

Let us analyse the circuit as the switch is moved from B to A.

  Notice how the output does not change as the switch bounces.

There is one disadvantage about the S – R bistable circuit, and that is what happens when both the inputs are 0.  This is an indeterminate state and the output is not predictable.  We cannot say if the bistable will return to the SET or the RESET state.  We can avoid this by ensuring that the inputs are changed alternately.

  Question 3 What is the problem with there being an indeterminate state?  ANSWER

The D-type Flop-Flip

Latches can be used to act as memories, but have a major problem.  They can be what is called transparent.  If one of the inputs is high, and the other is connected to a clock impulse, the output will change as the clock pulses pass through.  Let us think about this more using the S – R latch (made from NOR gates).  Data is put in through the S input while the R input is connected to a square wave pulse generator as below.

This latch is active high, which means that it changes state when S or R goes high.  We start off with R low and S changing from low to high and back again.  The output Q is low.  Then we change R to high and this should give us a high at the output Q.  We get that initially, but when the input S goes low, the output goes low.  When it goes high, the output goes high as well.  This situation lasts as long as R stays high.  So we get the clock pulse passing through the latch, which is why we call it transparent.  This can be a nuisance in computers and other systems where data changes rapidly.

We can overcome this problem by using edge-triggering.  Bistables that use edge triggering are called flip-flops.  Flip-flops do not have this problem with being transparent.  The D-type flip-flop is the basic design unit for sequential circuits, which are circuits whose outputs change with time.  The symbol with the D-type flop-flip is shown.

We should note the following about the flip-flop:

• The outputs are complimentary.  When Q is 1, Q-bar is 0 and vice versa.

• Terminal S and R are there to set and reset the flip-flop.  Signals at these inputs take priority over the other two inputs

• The data input takes in the data, while the clock input takes in the clock pulses.  The triangle indicates edge triggering.  An upward pointing arrow indicates positive edge triggering, while a downward arrow shows negative edge triggering.

• CMOS flip-flops are active high, while many TTL flip-flops are active low.

  The behaviour of the flip-flop is shown.

When we send a pulse down the SET or RESET lines, the results can be shown in the truth table:

Question 4 What is meant by a circuit being transparent?  ANSWER

Click HERE to go to Shift Registers

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